How page faults are handled with Page Size Extension?
I was trying to understand the concept of Page Size Extension, used in x86 processor but was not able to relate it with the page fault mechanism. From my understanding, when a page fault occurs, the virtual address is written in a register and an error code is pushed onto the stack. But if we are using page size extension, then how does the page fault handler comes to know what page size needs to be allocated.Can anyone help me with this?
There is a bit in the page directory. Intel calls this the PS bit. (Page size?) If the bit is set, it is a large page. If clear, a small page. While Intel allows both page sizes to be in use simultaneously, I would wager that few OS implementations would support mixed page sizes.
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